Programming dsPIC Microcontrollers in PASCAL (Ebook) - MikroE

6.5 Operation of the output compare module in SLEEP or IDLE mode

6.5.1 Operation of the output compare module in SLEEP mode

When the device enters SLEEP mode, the system clock is disabled. During SLEEP, the state of the output pin OCx is held at the same level as prior to entering SLEEP. For example, if the output pin OCx was high and the CPU entered the SLEEP state, the pin will stay high until the the microcontroller wakes up.

6.5.2 Operation of the output compare module in SLEEP mode

When the device enters IDLE mode, the OCSIDL control bit (OCxCON<13>) selects if the output compare module will stop or continue operation in IDLE mode. If OCSIDL = 0, the module will continue operation only if if the selected time base is set to operate in IDLE mode (TSIDL = 0). If OCSIDL = 1, the module will discontinue operation in IDLE mode as it does for SLEEP mode.

NOTE: The input pins OCxFA and OCxFB during SLEEP or IDLE modes, if enabled for use, will continue to control the associated output pin OCx, i.e. disconnect the output pin OCx if they are low.

pic-microcontrollers-programming-dspic-in-pascal-chapter-06-image-10a

Fig. 6-10a Pinout of microcontroller dsPIC30F4013, output compare module pins marked

pic-microcontrollers-programming-dspic-in-pascal-chapter-06-image-10b

Fig. 6-10b Pinout of microcontroller dsPIC30F6014A, output compare module pins marked

Finally, a description is given of the output registers of the output compare module of microcontroller dsPIC30F4013.

NAME	ADR	15	14	13	12-5	4	3	2	RESET STATE
OC1RS	0x0180	Output Compare 1 Secondary Register							0x0000
OC1R	0x0182	Output Compare 1 Main Register							0x0000
OC1CON	0x0184	-	-	OCSIDL	-	OCFLT	OCTSEL	OCM<2:0>	0x0000
OC2RS	0x0186	Output Compare 2 Secondary Register							0x0000
OC2R	0x0188	Output Compare 2 Main Register							0x0000
OC2CON	0x018A	-	-	OCSIDL	-	OCFLT	OCTSEL	OCM<2:0>	0x0000
OC3RS	0x018C	Output Compare 3 Secondary Register							0x0000
OC2R	0x018E	Output Compare 3 Main Register							0x0000
OC3CON	0x0190	-	-	OCSIDL	-	OCFLT	OCTSEL	OCM<2:0>	0x0000
OC4RS	0x0192	Output Compare 4 Secondary Register							0x0000
OC4R	0x0194	Output Compare 4 Main Register							0x0000
OC4CON	0x0196	-	-	OCSIDL	-	OCFLT	OCTSEL	OCM<2:0>	0x0000

Table 6-1 Register map associated with output compare module

OCSIDL – output compare stop bit in IDLE state (OCSIDL=0 the module is active in 
         IDLE state, OCSIDL=1 the module in inactive in IDLE state)
OCFLT – PWM FAULT state bit (OCFLT=0 no FAULT occured, OCFLT=1 FAULT 
        occured, hardware reset only)
OCTSEL – Output Compare timer select bit (OCTSEL=0 TMR2 selected, OCTSEL=1 
         TMR3 selected)
OCM <2:0> - mode select bit of the Output Compare Module
     000 – Output Compare Module disabled
     001 - Single compare match mode, pin OCx driven high
     010 - Single compare match mode, pin OCx driven low
     011 -  Single compare match mode, pin OCx toggles
     100 - Dual compare match mode, single output pulse at pin OCx
     101 - Dual compare match mode, sequence of output pulses at pin OCx
     110 - PWM mode without fault protection input
     111 - PWM mode with fault protection input